Job Description
<p>The SOC/ASIC physical design engineer-backend, you will be collaborating with architecture, timing, and logic design teams making a crucial impact on delivering cutting edge IC/SOCs for customers on Earth and beyond </p><p><br></p><p><strong>RESPONSIBILITIES:</strong> </p><p><br></p><ul><li>Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks) </li><li>Develop/improve physical design methodologies and automation scripts for various implementation steps </li><li>Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs </li><li>Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution </li><li>Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop </li></ul><p><br></p><p><strong><span class=”ql-cursor”> </span>BASIC QUALIFICATIONS:</strong> </p><ul><li>Bachelorβs degree in electrical engineering, computer engineering or computer science </li><li>3+ years of ASIC and/or physical design flow development experience (internship and collegiate extracurricular engineering project experience qualifies) </li><li>Automotive electronic device experience </li><li>VLSI design tools working level experience </li><li>Excellent oral and written communication skills</li></ul>